Integrated circuit (IC) chips are often soldered to conductor patterns formed on a circuit board, which may be a ceramic substrate or printed wiring board, in a manner which both secures and electrically interconnects the integrated circuit chip to the circuit board. Terminals are formed on the lower surface of the IC chip such that, when the chip is registered with the conductor pattern, each terminal will individually register with a single conductor of the conductor pattern. A solder reflow technique is then typically used to reflow the terminals and metallurgically bond them to their respective conductors.
Due to the numerous functions performed by integrated circuits, a relatively large number of terminals are required to interconnect the IC chip to the conductor pattern. Furthermore, because the size of an IC chip can be as little as a few millimeters per side, the size and spacing of the terminals and the conductors must be closely controlled in order to properly align and mount an IC chip to the corresponding terminal pattern formed on its circuit board.
A method which is widely practiced by the industry for soldering IC chips to a substrate is the flip-chip bonding process. This process utilizes an integrated circuit flip chip, which is generally a monolithic semiconductor device having bead-like terminals, or solder bumps, provided on one face of the chip. The solder bumps form a bump pattern and serve as interconnects between the IC chip and its corresponding conductor pattern on the substrate to which the flip chip is to be soldered by reflowing the solder bumps.
As an example, a conventional flip chip bump pattern composed of eighty-eight solder bumps is arranged as a rectangular array with a row of twenty-two solder bumps to a side, with each row being adjacent an edge of the flip chip. In this particular example, each bump will have a diameter on the order of about 0.15 millimeter, and be spaced center-to-center about 0.30 millimeter from the nearest adjacent bumps. In order to properly register with the single row, rectangular arrangement of this particular bump pattern, the individual conductors of this flip chip's conductor pattern are also spaced about 0.30 millimeter center-to-center, and each will generally have a width on the order of about 0.1 to about 0.2 millimeter.
Because of the close placement of the solder bumps and conductors, the techniques used to pattern the bump and conductor patterns on the surface of the flip chip and to solder the flip chip to its conductor pattern require a significant degree of precision. The size and composition of the solder bumps must also be closely controlled to achieve the required reliability, bond integrity and electrical characteristics, while concurrently eliminating the potential for electrical shorting between adjacent solder bumps and adjacent conductors.
Another method which is widely practiced by the industry for soldering an IC chip to its substrate involves the use of a ball grid array package 10, such as that illustrated in FIG. 1. The ball grid array package 10 utilizes an IC chip 12 which is wire bonded to a daughter board 14 with a number of wires 18. The wires 18 are routed through the daughter board 14 to terminals, or pads 16, on the opposite surface of the daughter board 14. Similar to the flip-chip process, the pads 16 form a pad pattern and serve as interconnects between the integrated circuit chip 12 and its corresponding conductor pattern on a substrate.
A conventional pad pattern 20 for a ball grid array package is shown in FIG. 2. As shown, the pad pattern 20 is composed of 144 pads 16 which are arranged in a rectangular array of twelve pads 16 per side. In the example shown, each pad 16 has a diameter on the order of about 0.76 millimeter and is spaced center-to-center about 1.5 millimeters from the nearest adjacent pads 16. The pad pattern 20 is shown with its conductor pattern 22 in FIG. 3. In order to properly register with the pad pattern 20, the individual conductors 24 of the conductor pattern 22 are generally on the order of about 0.15 millimeter in width, and are spaced about 0.3 millimeter center-to-center. As a result, patterning the pads 16 on the surface of the daughter board 14, patterning the conductors 24 on the surface of the substrate to which the daughter board 14 is to be soldered, and soldering the daughter board 14 to the conductor pattern 22 also require a significant degree of precision. As with the flip chip process, the size and composition of the pads 20 must be closely controlled to achieve the required reliability, bond integrity and electrical characteristics, while concurrently eliminating the potential for electrical shorting between adjacent pads 20 and adjacent conductors 24.
However, as dictated by the dimensions and layout of the pad pattern 20 and the limitations of the techniques by which the pad pattern 20 and the conductor pattern 22 are deposited, only the 132 outermost pads 16 of the 144 available pads 16 can be accessed by a single layer conductor pattern. Specifically, additional conductors 24 cannot be routed to the centermost pads 16 because such conductors 24 cannot be accommodated within the already tightly-arranged conductor pattern 22. Accordingly, in order to utilize all of the available pads 16, it has been the practice to use two or more conductor layers, with vias formed between layers to gain access to some of the pads 16. However, this technique undesirably adds complexity and costs to the process.
While presently known techniques used to form the terminal and conductor patterns for flip chip and ball grid array packages are generally sufficient, it would be desirable to improve the fatigue life of the solder joints formed by the terminals with the conductors, and more specifically, the stress induced in the solder joints as a result of temperature effects and differences in coefficients of thermal expansion of the materials used. Notably, the fatigue life of the solder joints is approximately proportional to the distance between the center of the pattern and the outermost terminal. Therefore, reducing the outside maximum dimension of a terminal pattern would result in reduced stresses, and therefore an improved fatigue life. However, as noted above, the minimum size of the terminal patterns for flip chips and ball grid array packages is limited by the necessity to route a sufficient number of conductors to the individual terminals. In turn, the number of conductors which can be successfully routed to the terminals within a single layer conductor pattern is generally limited by the precision with which the conductors can be formed.
Accordingly, what is needed is an improved terminal pattern for integrated circuit devices such as flip chips and ball grid array packages, in which the terminal pattern is uniquely configured so as to accommodate a desired number of conductors, while having a smaller maximum width than a rectangular terminal pattern having the same number of terminals, such that the improved terminal pattern exhibits improved fatigue life as compared to the conventional rectangular terminal pattern.